`timescale 1ns/1ns

module sequence_test1(
           input clk ,
           input rst	,
           input	data	,
           //    input	[7: 0]	data_in	,

           output	reg	flag
           //    output reg [15: 0]	data_out
       );

parameter id = 4'd0;
parameter s1 = 4'd1;
parameter s2 = 4'd2;
parameter s3 = 4'd3;
parameter s4 = 4'd4;
parameter s5 = 4'd5;
parameter a1 = 4'd6;

reg [3: 0] stat;
reg [3: 0] next_stat;

always@(posedge clk or negedge rst)
	begin
		if (!rst)
			stat <= id;
		else
			stat <= next_stat;
	end


always@( * )
	begin
		if (!rst)
			next_stat <= id;
		else
			case (stat)
				id:
					begin
						if (data)
							next_stat <= s1;
						else
							next_stat <= a1;
					end
				s1:
					begin
						if (~data)
							next_stat <= s2;
						else
							next_stat <= a1;
					end
				s2:
					begin
						if (data)
							next_stat <= s3;
						else
							next_stat <= a1;
					end
				s3:
					begin
						if (data)
							next_stat <= s4;
						else
							next_stat <= a1;
					end
				s4:
					begin
						if (data)
							next_stat <= s5;
						else
							next_stat <= a1;
					end
				s5:
					begin
						if (data)
							next_stat <= s1;
						else
							next_stat <= a1;
					end
				a1:
					begin
						if (data)
							next_stat <= s1;
						else
							next_stat <= id;
					end
				default:
					next_stat <= id;
			endcase
	end

always@(posedge clk or negedge rst)
	begin
		if (!rst)
			flag <= 0;
		else if (stat == s4&&data==1'b1)
			flag <= 1;
		else
			flag <= 0;
	end
endmodule
